Why do these other designs not fit?

Did you try compiling your original kernel against Altera's reference Stratix V BSP (if it fits)? In fact, you should probably also try compiling it against Altera's reference Arria 10 BSP.

On Arria 10, routability is generally much worse than Stratix V since Altera has switched to Partial Reconfiguration through PCI-E (this adds numerous extra placement and routing constraints). It is getting better by each new version, but very slowly. Unfortunately, for Partial Reconfiguration, timing quality of the BSP also plays a very big part, while the board manufacturers generally aren't very interested in spending much time optimizing their BSP.

My recommendation is to try compiling your kernel against both of Altera's reference BSPs for Stratix V and Arria 10 (s5_ref and a10_ref which are shipped alongside with Quartus). If it did work on the reference Arria 10 BSP, then your problem is due to bad timing quality of the BSP and you should contact your board manufacturer. If, however, it also failed to route with Altera's reference BSP, then you should report it directly to Altera; they are looking for such cases to help improve their Arria 10 placer and router. You should probably also report your findings with the Matrix Multiplication example.