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Altera_Forum's avatar
Altera_Forum
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8 years ago

Why do these other designs not fit?

Dear all, I've got another question about why designs do not fit on our Arria 10 board . This time, the designs do not overly use resources. I've used --high-effort. The first kernel has ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Is your top level file in Verilog or VHDL? I have had this issue of design not fitting on the FPGA if I have a large number of buses (signals greater than 1 bit wide) as input or output ports. To overcome this, I exported the ports as Virtual pins in the QSF file (This is when I am doing unit level compilation, and pin assignments do not matter).

set_instance_assignment -name VITRUAL_PIN ON -to csi_clock_clk ( where csi_clock_clk is a port in the module)

All ports are exported the same way.