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Altera_Forum
Honored Contributor
Honored ContributorWho wins VERILOG_MACRO.qsf or `define.v?
I have a design which `includes a header file which has `defines for default mode, say:`define ASIC_VERSION 32'h00000001 I have an "override" in my .qsf to specify the FPGA build, say:set_glob...
Altera_ForumHonored Contributor
Honored ContributorI did indeed try the ifndef guard around the Verilog `defines - fails same regardless of load order.
Failure is the Warning (10886) cited above and the fact that I want the .qsf VERILOG_MACRO definitions to win - not the Verilog. Strangely, in the .flow.rpt it shows the definitions I want. I get the warnings and then in the actual implementation I see that Verilog won out.
