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Altera_Forum's avatar
Altera_Forum
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9 years ago

Who wins VERILOG_MACRO.qsf or `define.v?

I have a design which `includes a header file which has `defines for default mode, say:`define ASIC_VERSION 32'h00000001 I have an "override" in my .qsf to specify the FPGA build, say:set_glob...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Turns out it is load order - just like Verilog. You have to place your VERILOG_MACROs after your VERILOG_FILEs for it to win. ~Tom