Forum Discussion
New ContributorWhich Quartus Version has Viewing Connection/ Highlight Routing feature?
You have to find and highlight a path. You can search right in Chip Planner, but cross-probing is much easier. That's why I mentioned timing analyzer because that's the most common way of cross-probing a path into Chip Planner, but you can cross-probe from the RTL Viewer, the Technology Map Viewer, and others. Find the object or path, right-click, and select Locate -> Locate in Chip Planner. The "connectivity schematic" you mention is the resource property viewer/editor, which shows you how specific resources are used in your design (and you can make low-level changes to their use post-fit). When you select a particular resource in the device floorplan (or cross-probe a part of your design to the Chip Planner), this view shows that resource's details. Anything highlighted in blue is part of the resource that is being used by your design. Gray parts are unused.
What you've done here is located an individual resource instead of a path. Again, it's easiest to do what you want from the timing analyzer because you can select a path in a timing report and select Locate *path* in Chip Planner instead of just an individual resource like what you show in your screenshot.
New ContributorHi @sstrell , thanks for the detailed explanation.
For answering your question:
>> What are you wanting to do here?
Actually, I was a Xilinx User for the past 5 years and would like to switch to Intel FPGA but I'm not so familiar with the capability of Quartus tools compare to Xilinx. Hence, asking such a question.
In Xilinx Floorplanner, users can easily gauge the floorplan for the Logic Lock Region connectivity, logic to IO connectivity, and logic to logic connectivity as the screenshot below:
Below is the floorplan view in the Chip Planner:
The connectivity schematic is available on the small window in the Chip Planner, but I don't know how to make the Chip Planner to show the connectivity on floorplan view. Here is my Layers Settings:
The reason to have the connectivity view available in the flooplan is for ease me to have a gauge on how far/close between logic to logic , or logic to IO without get that information from timing report by running Timing Analyzer.
May I know how can I acheive this in the Chip Planner? Thanks in advance.
Super ContributorYou have to find and highlight a path. You can search right in Chip Planner, but cross-probing is much easier. That's why I mentioned timing analyzer because that's the most common way of cross-probing a path into Chip Planner, but you can cross-probe from the RTL Viewer, the Technology Map Viewer, and others. Find the object or path, right-click, and select Locate -> Locate in Chip Planner. The "connectivity schematic" you mention is the resource property viewer/editor, which shows you how specific resources are used in your design (and you can make low-level changes to their use post-fit). When you select a particular resource in the device floorplan (or cross-probe a part of your design to the Chip Planner), this view shows that resource's details. Anything highlighted in blue is part of the resource that is being used by your design. Gray parts are unused.
What you've done here is located an individual resource instead of a path. Again, it's easiest to do what you want from the timing analyzer because you can select a path in a timing report and select Locate *path* in Chip Planner instead of just an individual resource like what you show in your screenshot.
RKath4Hello,
I did according to your idea by cross-testing from a timing way in Timing Analyzer to the Chip Organizer, and presently I can see the network in that way, and it can show the different ways the web too.
