Honored ContributorHello, I'm using Quartus 14.1 and I'm still seeing some of the megafunctions using AHDL. I'm using a Cyclone V Native IP Core and some of the files it generates are AHDL and I'm not able to do an RTL simulation only a Functional simulation. Does anyone know when Altera will rid itself of this dead HDL?
Honored ContributorWhat device and what IP? I would have thought a simulation model could be generated too, as you're right, it's pretty useless if you can't simulate it.
Honored ContributorAll the new IP is in VHDL/SV now.
Legacy IP may be in AHDL, but they usually provide VHDL/Verilog simulation models (all megawizard IP can be generated in VHDL/Verilog) They will never drop support for AHDL - there are too many legacy products out there that use AHDL.
