When is it safe to use smart recompilation?

I am too busy to try to replicate the issue in a minimal example. All the information I can give at the moment is that the parameters are in a .vh file that is included in the project, and included in all the verilog modules. If I change a parameter in that file and smart compile the compilation only takes 2 seconds and produces no compilation report. I haven't confrmed this, but from the behaviour after a smart compilation I suspect that the parameter change is ignored completely so the design runs with the old parameters unless I do a full compilation. Maybe smart compilation doesn't account for changes in .vh files.