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SAbde7's avatar
SAbde7
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

When is it safe to use smart recompilation?

When I turn on smart compilation and then change a parameter in the design(just a constant value stored in a register or a constant connected to combinational logic of fixed length like and adder or ...
SAbde7's avatar
SAbde7
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

I am using Quartus Prime 18.1 standard edition. I did not simulate the design after each of the compilations. I already had the expected results so I just loaded the design on the FPGA and compared. After a change of the parameters and a a smart compile the FPGA results deviated from the expected results, while doing a full compile after changing the parameters produced FPGA results that matched the expected results.