when I generated PLL ip before, a file name _inst.v was generated, so I can copy the example to my script. but the new one in quartus 17/18, the file seems missing. where can I find the example file?

Hi Zen, Please follow the below steps, 1. "File" Menu -> "Open"-> PLL.v(IP created file) 2. Then Go to "File" ->"Create/ Update" -> "Create Verilog instantiation Template files for current file" 3.Check the "PLL.inst.v" file under project directory. Let me know if this has helped to resolve the issue. Regards, Vikas