Forum Discussion
Altera_Forum
Honored Contributor
8 years agoIll just clarify:
always @(posedge clk)
begin
A<=0;
if (sel==0)
A<=in_u;
else
A<=in_v;
end
is identical to this:
always @(posedge clk)
begin
A<=in_v;
if (sel==0)
A<=in_u;
end