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Altera_Forum
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11 years ago

What we can do to fix the timing failure inside the Altera IPs?

I have design which use multiple DDR3 UniPHY controller in the qsys system. I compiled the design and the design failed timing. I checked the failed paths, and I can see some paths are inside the DDR...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Assume that the Altera IP is perfect, and even if you had written the module yourself with intimate understanding of all the inner workings, at this stage no further source modification would have any impact at all on your result. This sets you up mentally to go about fixing the problem using all of the other techniques and tools from the training and documentation.

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In my design, I did use a Avalon-MM to connect Nios as master, then another side, conects with multiple clock crossing bridge then DDR3 controller. But I don't understand what you mentioned "at this stage no further source modification would have any impact at all on your result", do you mean in this case, the modification in RTL level won't help, I have to use tool to have a better job in synthesis, fitter?

Thanks.