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I agree " overall design and constraints may also affect fitting inside ips", but it seems is difficult to conclude a common way that how to fix when we confront the timing issues inside IPs.
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Assume that the Altera IP is perfect, and even if you had written the module yourself with intimate understanding of all the inner workings, at this stage no further source modification would have any impact at all on your result. This sets you up mentally to go about fixing the problem using all of the other techniques and tools from the training and documentation.
For what it's worth, your requirements and description of your system isn't very clear, but if you're talking about having multiple DDR3 soft controllers inside a single Qsys system, one common trick is to put Avalon-MM pipline and/or clock crossing bridges in front of the DDR3 avalon slave port.
My experience has been that Fmax in the soft DDR3 may be higher when connected only to a single master.
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