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Altera_Forum
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11 years ago

What we can do to fix the timing failure inside the Altera IPs?

I have design which use multiple DDR3 UniPHY controller in the qsys system. I compiled the design and the design failed timing. I checked the failed paths, and I can see some paths are inside the DDR...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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some ips allow you pipeline settings of your own or even fool it with higher clk speed. Your overall design and constraints may also affect fitting inside ips.

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I agree " overall design and constraints may also affect fitting inside ips", but it seems is difficult to conclude a common way that how to fix when we confront the timing issues inside IPs.