Honored ContributorHi,
Could you explain to me the "left" of this code ? signal reset : std_logic_vector(15 downto 0) := (others => '1'); reset <= reset(reset'left - 1 downto 0) & "0"; Thanks Jennifer
Honored Contributorsignals have attributes.
you may read more in books "Circuit design in VHDL", "VHDL progamming by example" and so on. if you have vector with definition like above LEFT attribute should return 15 , and in this case it is equal to value of HIGH attribute if you will have declaration reset : std_logic_vector(0 to 15) then LEFT return 0 which equal to value of LOW attribute, but HIGH and RIGHT return 15. if you concatenate bit to vector => use single quote for bit, '0' instead of "0" for exclude misleading, possible errors.Honored ContributorHi,
I just want to add three links which explains the attributes: https://books.google.co.uk/books?id=yt3ccaaaqbaj&pg=pa395&lpg=pa395&dq=vhdl+signal+attributes+table&source=bl&ots=mzlvsrj-mg&sig=jmre0dsfgxaawvhyfzczdlfat2m&hl=de&sa=x&ved=0ahukewiv07qxl_tjahvf7w4khajhbdmq6aeipdae#v=onepage&q=vhdl%20signal%20attributes%20table&f=false http://www.csee.umbc.edu/portal/help/vhdl/attribute.html http://users.ece.utexas.edu/~roth/book/ch8_slides.pdf Those should answer the questions related to attributes of signals in VHDL.
