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Altera_Forum
Honored Contributor
Honored ContributorWhat it means ? 'left
Hi, Could you explain to me the "left" of this code ? signal reset : std_logic_vector(15 downto 0) := (others => '1'); reset <= reset(reset'left - 1 downto 0) & "0"; Thanks Je...
Altera_ForumHonored Contributor
Honored ContributorHi,
I just want to add three links which explains the attributes: https://books.google.co.uk/books?id=yt3ccaaaqbaj&pg=pa395&lpg=pa395&dq=vhdl+signal+attributes+table&source=bl&ots=mzlvsrj-mg&sig=jmre0dsfgxaawvhyfzczdlfat2m&hl=de&sa=x&ved=0ahukewiv07qxl_tjahvf7w4khajhbdmq6aeipdae#v=onepage&q=vhdl%20signal%20attributes%20table&f=false http://www.csee.umbc.edu/portal/help/vhdl/attribute.html http://users.ece.utexas.edu/~roth/book/ch8_slides.pdf Those should answer the questions related to attributes of signals in VHDL.
