Honored Contributor
Honored ContributorHi,
in order to understand what is really going on on the address lines to the SRAM, I made some Signal Tap measurements. The results are a basis for a new discussion: In the attachment I put three screenshots. One shows the SRAM test with the IOWR_32DIRECT macro used. I write 32 bit testdata at the first 16 addresses of the SRAM (0x00 - 0x0F). Everything works as expected. The SRAM is addressed from 0x00 to 0x0F and the data is succesfully written. The second screenshot shows the SGDMA transfer of also 16 write cycles. It is very impressive to see that in the view with the same scale as the IOWR_32DIRECT view, the performence is very much improved. The third screenshot is zoomed into the SGDMA transfer. There, one can see that the first two addres bits are unused which leads exactly to the behaviour that I've described earlier when I read the SRAM back with IORD_32DIRECT. BUT, I don't understand why the SGDMA behaves this way (even if I look at your last post from yesterday). My SRAM has a size of 512kx32 which I never can fully use with this kind of addressing mode the SGDAM is doing. However, if I use the _32DIRECT macros, I do can use the whole memory space. You are right that if I do the addressing in the IORD_32DIRECT macro like this: (SRAM_BASE, 4*offset), I can read the correct values that the SGDMA has written to the meory but all in all I can only use a quarter of the available memory of my system. If I'm wrong at some point or if there is a solution for this problem, please let me know. Regards, Maik
