What is/are the right SOPC compenent(s) for my project?

A x32 SRAM that has 19 address bits should cover 2MB of data storage space. They only provide 19 bits instead of 21 because they provide byte enables as well. So when the access goes off-chip to the memory the address is supplied as a word address and the individual byte lanes for each word are accessed using the byte enable signal to qualify the writes.

So the behavior in SOPC Builder is that all addresses provided by a master are byte addressed. All addresses into a slave are word addressed with byte lanes controlled by the byte enable signal. This means that the access Nios II performs to the fabric should always be an address that is a multiple of 4 (i.e. the two LSBs are always low) and the byte enables control the lanes being accessed. Since the memory uses word addressing what the fabric does is takes the Nios II address line and performs a right shift of two bits and sends that into the slave port of the memory. The idea of the Avalon specification is you just need to follow it for masters and slaves and not have to care about what it is doing internally.

The reason why the master needs to use byte addressing is because you can have different width masters in your system so if everything was word addressed the increments necessary for each master would map to different locations in memory.

This read "IORD_32DIRECT(SRAM_BASE, 0x01)" will most likely alias into offset 0 of the SRAM because the fabric will take the 0x1 and shift it right two bits resulting in an SRAM word address offset of 0. The same aliasing would happen if you use IORD_32DIRECT for offsets 2 and 3 as well, both of those should alias into address 0 which is not what your intention is. Really at the end of the day if you stick to byte addresses in your C code, the pointers you send to the DMA, specify the transfer length in bytes (four bytes for every ADC word) you should end up with a working system.