Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThis toppic bothers me so much that I have to discuss this a little bit further even if it's a quarter past 9 in the evening . . . ;-)
I still don't understand this behavior. I have a SRAM memory that has 19 address bits which defines a memory addres space from 0 to 524287. My memory data sheet tells me that at each address I can put 32 bits of data (+ some bits for parity, etc). This leads to a total memory size of 524287 * 32 bits -> 16,7Mbit which is 2MByte which is exactly what I told my hardware designer what I want to have . . . So when I use my _32DIRECT macros I still belive that when I write at address SRAM_BASE + offset, that I write 32 bits of data at this very addres. And this I think I can do up to 524287. If I increase the address by 1 I really belive that I'm on the next address to write the next 32 bits. But maybe I'm totally wrong on this which I will try to confirm this, tomorrow. I also don't understand, why I can read like this from the SRAM: IORD_32DIRECT(SRAM_BASE, 0x01) and get the data that I have written with IOWR_32DIRECT(SRAM_BASE, 0x01, 0x01), wheras If I write IORD_32DIRECT(SRAM_BASE, 0x00) or IORD_32DIRECT(SRAM_BASE, 0x04) I get the full 32 bit of data the SGDMA has written. Somehow this is not clear to me . . . .