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Altera_Forum
Honored Contributor
15 years agoI believe so. If you pass in offsets 0, 1, 2, 3, 4, 5, etc... to the cache bypassing _32DIRECT macros what I would expect is aliasing/undefined behavior since the CPU and fabric do not support unaligned accesses. So the DMA in x32 bit configuration with stride turned off (stride = 1) is supposed to walk through the memory space starting at byte offset 0, then 4, 8, 12, 16, etc...
The first word from your ADC will be placed at address 0x0-0x3 The second word from your ADC will be placed at address 0x4-0x7 The third word from your ADC will be placed at address 0x8-0xC etc... The last access would be at address "length-4" - "length -1" assuming the entire transfer started at address 0x0