What is/are the right SOPC compenent(s) for my project?

125MHz is doable on Cyclone III, especially with a fast speed grade device (I've hit around 180MHz using a -6 speed grade). Since your samples come it at 80MHz, that's the maximum fill rate to the memory. So bumping up the ADC and everything else isn't really going to speed up how fast you can fill the memory since the ADC won't be able to keep up. Since you plan on doing FFT in software you'll need all the performance you can get as it's really slow that way.

So if you keep the CPU and SRAM on the same domain and clocked it as high as possible that will give you the most software computational throughput. Things like streaming data, DMAs, etc... usually are not affected by latency so if you did your clock crossing there then you will be able to keep the CPU clocked fast and with low latency access to SRAM as well as isolating the other logic to some other clock domain. If you have a lot of stuff mastering SRAM you may find the fanin-out reduces the Fmax and that's where inserting pipeline bridges may be needed. Here is a doc you can take a look at for more details: http://www.altera.com/literature/hb/nios2/edh_ed5v1_03.pdf