What is/are the right SOPC compenent(s) for my project?

Since ADCs have many different interfaces it is not included as a standard component in SOPC Builder. Creating a new one is pretty easy though since it's just a FIFO for the most part.

The modular SGDMA can be used and modified in any project. It's offered as a design example so that users have an alternative to the SGDMA that's shipped with SOPC Builder. Since it's modular you can implement variant DMAs easily by re-using the master logic and just replacing the controller (dispatcher). The master blocks are the difficult ones to implement due to all the features and the tuning that's involved so usually the customization is left in the controller portion of the DMA. If you copy the IP directory from the design example into your own project then the cores will appear the next time you open SOPC Builder in the category "Modular SGDMA".

The SRAM component must be on the same clock domain as the tri-state bridge so if you want to operate the Nios II core on a different clock domain then the clock crossing bridge would need to be between the tri-state bridge and CPU (at a minimum). One question, does the CPU need to access the sampled data in memory? I ask because any time you introduce clock crossing you increase the memory read latency by around 12 clock cycles so if you are looking to process the samples you would probably be better off keeping the CPU on the same domain. Examples will be hard to find since cranking up the memory latency is normally bad for embedded systems.