Forum Discussion
Altera_Forum
Honored Contributor
15 years agoOkay, next thing I'm thinking about is that my Nios runs with =<50Mhz and the ADC/SGDMA/SRAM part of the system runs with a different clock speed (here 80Mhz).
I think I need a clock crossing component in my SOPC design. Where do I have to connect this? Between the SRAM component and the CPU or between the Tristate Bridge and the CPU? I havn't found any according SRAM examples on the net . . . Maik