What is/are the right SOPC compenent(s) for my project?

That's pretty much how I would do it. The only component you are missing is the ADC. You can probably make a component comprised of the dcfifo megafunction which is clocked at whatever your sample rate is offchip and your system speed on the other side. You would export the sampling side using a conduit and map the other side to a streaming source port that you would connect to the SGDMA in ST-->MM mode.

To do the flow control on the ST side of the FIFO you can drive the ST valid signal using 'fifo not empty'. The ST ready coming into the interface you would logically AND with 'fifo not empty' and use that to drive the readack signal of the FIFO. Make sure to put the FIFO into lookahead mode so that you can keep the ST ready latency down to 0.

Here is the Avalon spec for more details: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

The SGDMA can trigger the interrupt at the end of each descriptor chain. Each descriptor in the chain can describe up to 64kB in payload size. If you want to send more data than that then just chain a bunch of descriptors together. Alternatively you can use this which has a simpler programming model: http://www.altera.com/support/examples/nios2/exm-modular-scatter-gather-dma.html?gsa_pos=1&wt.oss_r=1&wt.oss=modular