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Altera_Forum's avatar
Altera_Forum
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12 years ago

What is the mean of "Assertion misses" and "Assertion hits" in Modelsim sim tab?

When I do simulation in Modelsim, in sim tab, there are "Assertion misses" and "Assertion hits", I attached a screenshot to show it, what is the mean of this? Thanks in advance.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

In VHDL, an assertion hit is an assert statement that did not fail. A miss is an assert statement that failed at least once. The words pass and fail are not used because in other languages, it possible to have the assertion pass, but still not considered a hit. (a vacuous pass) And an assertion that does not ever execute can be a miss.