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In Altera ALTLVDS Mega function setting, if I dont enable this option
"Implement Serializer/Deserializer circuitry in logic cells".
What's the maximum data rate of ALTLVDS? (Stratix III)?
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Read the handbook. The maximum speed depends on the speed grade you get. The high-end speed grades operate at greater than 1Gbps.
If you implement the SERDES in logic cells, then the rate is probably around 600Mbps.
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Or how many dedicated SERDES circuitry in the Stratix III device ?
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Check the handbook. It lists how many 'dedicated' LVDS SERDES channels there are. Be careful when you interpret the numbers, sometimes the totals include 'emulated' LVDS.
You can also create a project in Quartus and look at the pin planner view of the device. That'll show you where the LVDS pins are on the part.
Cheers,
Dave
Honored Contributor
