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Altera_Forum
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13 years ago

What is mean of reset assertion and deassertion?

When I read a textbook about FPGA design, it mentions reset assertion and deassertion. But I can't understand what the mean of assertion and deassertion. Anybody can explain them for me?

Thanks very much!

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    When I read a textbook about FPGA design, it mentions reset assertion and deassertion. But I can't understand what the mean of assertion and deassertion. Anybody can explain them for me?

    Thanks very much!

    --- Quote End ---

    Reset assertion is when the reset is logically 'true'; deassertion is when it is logically 'false'. The point where reset changes from 'true' to 'false' is generally important since it must be made to happen at a time that is synchronous to the clock so that those signals that use reset don't have their timing requirements violated.

    Kevin Jennings