What is mean of reset assertion and deassertion?

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When I read a textbook about FPGA design, it mentions reset assertion and deassertion. But I can't understand what the mean of assertion and deassertion. Anybody can explain them for me?

Thanks very much!

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Reset assertion is when the reset is logically 'true'; deassertion is when it is logically 'false'. The point where reset changes from 'true' to 'false' is generally important since it must be made to happen at a time that is synchronous to the clock so that those signals that use reset don't have their timing requirements violated.

Kevin Jennings