What I did Wrong in my Verilog Project? (Quartus cannot compile it)

You have several issues in the below code:

- it's combinational (no edge sensitive condition)

- CurShiftData is the RAM output register and a shift register at the same time. That doesn't work.

Because I don't know what you actually wan to achieve here, I can't suggest a solution.

always @(OutClock)
begin
  begin
    {CurShiftData, OutData}<=CurShiftData;
  end
  if(CurPos) CurPos<=CurPos-1'b1;
  else
  begin
    CurPos<=79;
    CurShiftData<=EndPos;
    if(EndPos==0 && EndPosSw)
    begin
      CurShiftData=TimeStep];
      EndPosSw=0;
    end
    else
    begin
      CurShiftData=RingData;
      EndPosSw=1;
      EndPos=EndPos+1'b1;
    end
  end
end