What exactly is essence of "Library Mapping" in ModelSim, map to what and why?

I think you are slightly confusing packages and libraries. Packages and design unit/entities exist inside libraries. VHDL defines logical libraries, and a tool maps a logical name in the language to a physical place in an OS filesystem. VHDL allows you to compile different architectures (like RTL-level and Gate-level) of the same unit into different logical libraries. So if you have 5 instances of the same unit in one design, you can have 4 of them use the RTL version and the other use the gate-level for better simulation performance. You can also choose different architectures to tweak synthesis results. Modelsim lets you do this for Verilog designs as well, but it was outside of the scope of the language until SystemVerilog came around.