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When do we map libraries and why, when we create a Quartus II project why do we still need to create a new library?
I am completely new to the whole ModelSim thing and am confused about this issue at present.
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VHDL defines the use of libraries for reuseable code. If you've ever coded in C, the analogy is that when you want to reuse C-code, you create a header file with the functions to re-use in other code, and a C-file (or multiple files) containing the implementations, that code can then be compiled into a static or dynamic library for linking against your application code. In Modelsim, the compiled library exists within a library folder, and the library can be re-used by multiple designs. Quartus does not respect libraries, and just compiles everything into a common internal library (Quartus will accept library syntax, but it doesn't really do anything useful with it).
For example, when using Modelsim, the lines
library ieee;
use ieee.std_logic_1164.all;
allow you to use the std_logic_vector type. You can create create your own library and build code into it via commands like
vlib mylib
vmap mylib /mylib
vcom -work mylib mycomponent_pkg.vhd
vcom -work mylib mycomponent.vhd
where the mycomponent_pkg.vhd file contains a package with the component declaration (analogous to a .h header file when coding in C), and mycomponent.vhd contains the implementation (analogous to a .c file).
In your top-level design (analogous to your c application code), you can then access your component via
library mylib;
use mylib.mycomponent_pkg.all;
and then create an instance of mycomponent.
Bottom-line is that its an organizational feature implemented in VHDL, ignored in Verilog, and (I think) picked up in SystemVerilog.
Cheers,
Dave
Honored Contributor
