New Contributor
ContributorHi Dolemy,
As FvM said, you can refer to the "Chapter 7 PLL in Cyclone II Devices" in Cyclone® II Device Handbook to learn more about PLL architecture.
From Table 7.2 in this handbook, you can find out the highest division figure that PLL can provide. Further Restrictions could also be related to VCO frequency etc, which you can also find out in this chapter.
Some Intel FPGA devices' PLL can do "cascading", which makes a much higher Clock Division. But for Cyclone II device on this DE2 board, PLL cascading is not mentioned in the feature list. I will try in Quartus and see if it is possible to do cascading.
Cyclone® II Device Handbook: https://www.intel.com/content/www/us/en/content-details/654376/cyclone-ii-device-handbook.html?wapkw=cyclone%20II%20handbook&DocID=654376
Thanks & Regards,
Xiaoyan
New ContributorThank you for your answer.
I read the Handbook according to your answer and solved the problem.
My problem was that cyclone ii supports a lower number of division and multiflier factors than I thought.
In the end, I added a separate circuit to my project to achieve my target clock
. Thanks to your answer, I was able to solve the problem. Thank you
ContributorHi there,
Good to know my answer helps!
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Best regards,
Xiaoyan
New ContributorOf course!
But I don’t know where to do a survey.
Can you tell me how?
