Weird negative logic issues

Well I fixed that problem somehow, but I have another one. My write signal is working but if I don't put in the output so that I can see my write enable signal it misses the first nib. If I just put in the output signal, it gets the first nib. I don't see why the presence or absence of a test signal should influence the result.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
--This version starts storing frames at address 0, so you can store a bunch of frames and then send them all out at once
entity framestore is
	port
	(
		clk,reset : in std_logic;
		input: in std_logic_vector(3 downto 0); -- the input ethernet frame
		valid: in std_logic; --valid signal that comes with input
		readEN: in std_logic; --high when we want to read from memory
		wrenout: out std_logic;
		output : out std_logic_vector(3 downto 0) --output, has value if we're reading
	);
end framestore;
architecture structure of framestore is
	signal holdout: std_logic_vector(3 downto 0);
	signal address: std_logic_vector(14 downto 0);
	signal next_address: std_logic_vector(14 downto 0);
	signal regRead: std_logic;
	signal regValid: std_logic;
	signal readEN_RE: boolean;
	signal valid_FE: boolean;
	signal wrenframe: std_logic;
	signal counter: integer range 0 to 23;
	
	component ram4bits is
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (14 DOWNTO 0);
		clock		: IN STD_LOGIC  := '1';
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
	end component;
begin	
	process(clk,reset,valid,readEN)
	begin
		if(reset = '1') then
			next_address <= "000000000000000";
			regRead <= '0';
			regValid <= '0';
		elsif(clk'event and clk = '1') then
			regRead <= readEN;
			regValid <= valid;
			if(readEN_RE) then
				next_address <= "000000000000000";
			elsif(valid = '1' or readEN = '1') then
				next_address <= address + '1';
				counter <= 0;
			elsif(valid_FE or counter > 0) then
				counter <= counter + 1;
			end if;
			if((valid = '0' and readEN = '0' and counter > 0) or valid_FE) then
				next_address <= address + '1';
			end if;
			if(counter = 25) then
				counter <= 0;
			end if;
		end if;
	end process;
	
	store: ram4bits port map(address,clk,input,wrenframe,holdout);
	
	readEN_RE <= regRead = '0' AND readEN = '1';
	valid_FE <= regValid = '1' AND valid = '0';
	wrenframe <= '1' when (valid = '1' or counter > 0 or valid_FE) else '0';
	output <= holdout when readEN = '1' else "0000";
	address <= next_address;
	
	wrenout <= wrenframe; --this is the line that makes things work if it's present
end structure;

I resolved it. Not sure how

To allow other users to reproduce the problem exactly as you experienced it, it would be a good idea to pack the example design with a test *.wvf file to a quartus archive and post it here.

I don't see the issue right away, but you might try removing everything but clock and reset from the sensitivity list in the process. I also notice that the signal 'counter' is not assigned during reset.

how do you know what to put in a sensitivity list? I figured it'd be easier to do it all in one block because then I'd have repeated code in places.

Thanks, I'll work on that