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Altera_Forum
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16 years ago

Weird negative logic issues

I'm trying to write a stream of data into SRAM in the following way. When valid data comes in, I want to write it to memory. When valid is deasserted I want to write 12 bytes of 0's to memory. I'm...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I don't see the issue right away, but you might try removing everything but clock and reset from the sensitivity list in the process. I also notice that the signal 'counter' is not assigned during reset.

For general readability you should try to just assign one output per process - so your code would have 4 processes. It will make your life much easier. :)