Weird: Different results just by hitting "Start Compilation"

I don't believe LAI by itself should, since I don't think it uses JTAG.

1) I would recommend checking if it is changing by looking at the slacks.

2) Although it shouldn't, again it probably doesn't matter. Every time you make a change it will be a different compile, and so if there's a marginal problem in the design that might or might not work compile to compile, it's more important to find that problem than worry that the compile might change. Of course, if you can't repeat it there's not much you can do.

3) If you do repeat it, and want to spend the time debugging it, then I make a copy of the entire project with /db. I set the top level partition to post-fit, which locks the placement and routing down, and add SignalTap to start looking at these post-fit nodes, trying to find what's wrong. It can be time consuming, but should get you there without the problem ever disappearing because you recompiled. (You will run a full compile, and it will preserve all of your logic while re-synthesizing/fitting the SignalTap logic, so the compiles should be much quicker too). I don't know if this works with LAI, to be honest, but think it should.

4) Since it doesn't meet timing, that is another concern. If it's off by a decent amount, that could easily be it, and rather than investigating why, it's worth spending the time to get it to close timing. Heck, it's worth spending that time regardless.

5) As for the timing constraints, I don't use set_max_skew for source synchronous as they're not exactly correct. (For example, it compares the skew between data pins, which you don't care about. You only care about skew between data and clock). I have a document on alterawiki about source-synchronous interfaces. That being said, what you have probably works fine and is quick and easy, so unless you suspect there are problems with the LAI, it's probably fine to leave as-is. The LAI won't be part of the final design, so you just need it to work under lab conditions, which I'm guessing it easily does. (Source-synchronous interfaces can be hard to constrain, and sometimes hard to close timing, but they're surprisingly robust in the LAB. I've seen cases where the constraints were way off, and the fitter was doing the wrong thing, and it still worked in hardware in the lab)