Honored Contributor
Honored ContributorMy design should be fully constrained. At least the Compilation tells me so and there is nothing unconstrained in the "Unconstrained Path Report". But I must confess that some of my Timing requirements doesn't meet.
Oh, and yes, I test it on running hardware (hoooraaaaay!!) ;-). My speed-optimized Design works just fine, and after recompiling the power-optimized design (I did this several times now) every design ended in a functional device. It was only the very first compiler-result which didn't work. You noticed the /db folder. Isn't it possible that Quartus makes some changes there while compiling? Actually there are some files with new date and timestamps. I am using the Logic-Analyzer-Interface. May this affect the changings you noticed on the SignalTap Logic Analyzer? Besides, I know you're a pro in .sdc-Files. Are this good values for a Source-Synchronous Interface (Single-Data-Rate)? set_max_skew -from [get_ports {SERDES_RD [*]}] -to * 0.500 set_max_skew -from * -to [get_ports {SERDES_TD [*] SERDES_Clk}] 0.500 set_max_skew -from * -to [get_keepers {altera_reserved_lai*}] 0.500
