Forum Discussion

Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Ways to improve timing on Top module?

Say I have 3 modules: 1) Top module 2) sub-module A-(achieved freq 150Mhz when compiled separately) 3) sub-module B-(achieved freq 200 Mhz when compiled separately) After I instantiate sub-...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


What is your interconnect usage? Designs with an average value below 50% typically do not have any problems with routing. Designs with an average between 50-65% may have difficulty routing. Designs with an average over 65% typically have difficulty meeting timing unless the RTL tolerates a highly utilized chip. Peak values at or above 90% are likely to have problems with timing closure; a 100% peak value indicates that all routing in an area of the device has been used, so there is a high possibility of degradation in timing performance.


Thanks.

Best regards,

KhaiY


Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Hi Khai,

Average interconnect usage (total/H/V) 50.7% / 48.7% / 57.0%
Peak interconnect usage (total/H/V) 80.4% / 81.7% / 86.1%
Since average interconnect is less it should not cause any problems in routing right ?
But 8 out of 10 times fitter terminates because of routing congestion.
Is there a way to find which module has high interconnect usage ? So that I can change the coding style and improve timing .
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Yogesh,

    Yes. There is a way to check which module uses most of the routing resources.

    Thanks.

    Best regards,

    KhaiY

     

    • Yogesh's avatar
      Yogesh
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi Khai,

      I think the screenshot you shared is for quartus pro edition. I am using intel quartus standard edition 18.1

      I find only routing usage summary under logic and routing section ,which only talks about resources like Block interconnects
      C12 interconnects
      C2 interconnects
      C4 interconnects

      and not about module level usage . Is there someother option to check the same w.r.t each module of my project?

      thankyou

      regards,

      Yogesh

      • KhaiChein_Y_Intel's avatar
        KhaiChein_Y_Intel
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        Hi Yogesh,

        The report in the Pro edition is different from the Standard edition. In this case, you have to check the routing utilization in the Chip Planner.

        Thanks.

        Best regards,

        KhaiY