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Altera_Forum's avatar
Altera_Forum
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9 years ago

Way to switch codes by the compilers

Hello, guys.

I am in the VHDL, and I am using the Quartus with the ModelSim.

I have written a clocker for the simulations; 

library ieee;
use ieee.std_logic_1164.all;
entity clocker is
    port (
        clock: out std_logic
    );
end;
architecture clocker of clocker is
    constant clock_period: time := 1 ps;
begin
    process
    begin
        clock <= '0';
        wait for clock_period;
        clock <= '1';
        wait for clock_period;
    end process;
end;

and I have used the "generate"s and switch by one constant value; 

-- DO NOT FORGET to toggle when switched to the other compiler.
constant simulating: boolean := true;
...
g0: if not simulating generate
    clock <= CLOCK_125_p;
end generate;
g1: if simulating generate
    c0: clocker
        port map(clock);
end generate;

But I began to think gradually that I want to switch codes by automatically.

For example, in the C/C++, below snippet (maybe) has the ability. 

#ifdef __GNUC__# ifndef __clang__
// codes for the gcc...# else
// codes for the clang...# endif# endif

Finally, I have written the snippet to switch that. 

-- synthesis read_comments_as_HDL on
-- constant simulating: boolean := false;
-- synthesis read_comments_as_HDL off
-- synthesis translate_off
constant simulating: boolean := true;
-- synthesis translate_on

It has works on the quartus_map(Quartus), and the vcom(ModelSim), but I think it is not clever way.

Question: How should I write? Where is a good way?

Environment Info:

Windows 7 Ultimate Service Pack 1

Quartus Prime Version 16.0.2 Build 222 07/20/2016 SJ Lite Edition

ModelSim ALTERA STARTER EDITION 10.4d Revision: 2015.12

Cyclone V GX Starter Kit (5CGXFC5C6F27C7)

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Like I told you in your previous post - the synthesis directives are not part of the VHDL language and only have meaning to synthesis tools, hence why they do nothing and are ignored by modelsim, and all other simulators. VHDL has no pre-processor to do what you're trying to do.

    The usual method is to just have the clock is just to have it as an input to the DUT, and then generate the clock in the testbench. So in your case, why cant you just connect your CLOCK_125_P to a signal in your testbench?

    PS. I would not recommend reconnecting a clock inside a module, as you can run into delta cycle problems in simulation. Try simulating this code - and see if you see anything odd: 

    
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mad_clock is
end entity mad_clock;
architecture test of mad_clock is
  signal clock  : std_logic := '1';
  signal clock2 : std_logic;
  
  signal count  : unsigned(7 downto 0) := x"00";
  signal count2 : unsigned(7 downto 0);
begin
  process(clock)
  begin
	if rising_edge(clock) then
		count <= count + 1;
	end if;
  end process;
  
  clock2 <= clock;
  
  process(clock2)
  begin
	if rising_edge(clock2) then
      count2 <= count;
	end if;
  end process;
  
end architecture test;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Thank you reply.

    > Like I told you in your previous post...

    Umm, I will have not understood that exactly...

    > The usual method is...

    I had misunderstood that it would not recommend to "call" the "main" module by the other modules, and it is the top-level entity.

    I can connect in the testbench. Why have not I done that...

    > PS...

    I have not known the delta cycle problems.

    I will watch out, thank you teach me.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Your replies still imply you think this is software.. it is not, it is hardware.

    Modules/entities are not called, they are instantiated, like placing a chip in a circuit.