Way to switch codes by the compilers

Like I told you in your previous post - the synthesis directives are not part of the VHDL language and only have meaning to synthesis tools, hence why they do nothing and are ignored by modelsim, and all other simulators. VHDL has no pre-processor to do what you're trying to do.

The usual method is to just have the clock is just to have it as an input to the DUT, and then generate the clock in the testbench. So in your case, why cant you just connect your CLOCK_125_P to a signal in your testbench?

PS. I would not recommend reconnecting a clock inside a module, as you can run into delta cycle problems in simulation. Try simulating this code - and see if you see anything odd:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mad_clock is
end entity mad_clock;
architecture test of mad_clock is
  signal clock  : std_logic := '1';
  signal clock2 : std_logic;
  
  signal count  : unsigned(7 downto 0) := x"00";
  signal count2 : unsigned(7 downto 0);
begin
  process(clock)
  begin
	if rising_edge(clock) then
		count <= count + 1;
	end if;
  end process;
  
  clock2 <= clock;
  
  process(clock2)
  begin
	if rising_edge(clock2) then
      count2 <= count;
	end if;
  end process;
  
end architecture test;