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Hi,
As general advice, is it considered better to work with std_logic_vector or integer? I was originally trained in hardware logic design so working with std_logic_vectors (a 'bus' of binary signals) seem like the right thing to do but over the years the amount of 'C' programming has become dominant so working with integers in VHDL is very enticing!!
Thanks for taking the time to help a VHDL beginner :-)
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It happened the same way for me, as I started off with TTL circuitry back in the seventies, and I made the transition from std_logic_vector to unsigned/signed only a year or so ago, dabbling with integers first ...
Unfortunately most VHDL textbooks focus on std_logic_vectors and integers. Integers look appealing but have their own peculiarities: they are usually limited to 32 bits, and if not constrained properly use 32 bits. With
ieee.numeric_std unsigned and signed are a valid alternative.
You're welcome!
Regards,
Josy
Honored Contributor
