Waveform Editor - odd inversion

Hi,

thanks for the advice about the libraries, I took out all the references to ieee.std_logic_unsigned.all whereupon all my if x = y statements failed so I then corrected them by casting my standard logic vectors to unsigned for the comparison.

Perhaps the 'unsigned' library was producing something that then confused the simulator.

As general advice, is it considered better to work with std_logic_vector or integer? I was originally trained in hardware logic design so working with std_logic_vectors (a 'bus' of binary signals) seem like the right thing to do but over the years the amount of 'C' programming has become dominant so working with integers in VHDL is very enticing!!

Thanks for taking the time to help a VHDL beginner :-)

regards

PhilipJ