Forum Discussion
Altera_Forum
Honored Contributor
9 years agoSorry, I condensed my code so as not to take up too much space, which might have led it to be a bit confusing.
I declare the variable Count as normal in architecture behavioral of <element> is signal Count: std_logic_vector(7 downto 0); ... begin ... if Count(4 downto 0) = 24 then .... end behavioral; The line you've highlighted is meant to simple take the bottom 5 bits of Count (it's an 8-bit counter) and see if it equal to '11000', I am still a relative novice with VHDL so please explain if I have misunderstood. regards PhilipJ