Watchdog Timer reset issue related to Onchip flash IP & dual config ip for Max10 Fpga Boiard

Hi,

we have performed following steps and got issues related to watchdog timer

1) Created 2 rpds file one as factory rpd and other as Application rpd with enabled watchdog while generating them.

2) Writing the rpds in CFM1(Factory rpd) and CFM0 (application rpd) resp.

3) Triggering CFM0 i.e Application we are getting readback reg value which confirms us that application is loaded. Sometimes works and fails other time. need to trigger multiple times. Why?

4) As watchdog is enabled, if watchdog reset doesn't happen then factory image will be loaded. Question : How timer values are calculated? Tried with multiple values of watchdog times in ICB settings. But doesn't make sense to me as it always covers up around a min.
5)Even cross checking status registers related to it is unclear.
6)we are not able to check the default driven values over stp.

7) cant see any signal over the model sim simulation as well.

Please give us detailed information to get more clarification for this issue if possible please mail me the example design for the same for max 10M08 Eval fpga board.