Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- When compiling my design i get the following warings. Warning: Timing-driven synthesis is skipped because there are multiple hierarchies in the design Warning: Timing-driven synthesis is skipped because it could not initialize the timing netlist I think this is the reason I am getting some timing issues with my design. What does it mean and how do I fix it. All help would be appreciated. --- Quote End --- Hi, looks strange. Are you using design partitions ? Is the SDC file in the project included? Which device are you using ? Kind regards GPK