warning "Rule c104" from sync chain (3x DFF)

i get the following warning: rule c104: clock signal source should drive only input clock ports (design assistant rule).

from a synchronization chain of 3 DFF's. Why is this? Is it false warning or something wrong with the design? I thought it's according to Alterra recommendation.

Using MAX II device. Quartus II 9.1.

file:///C:/DOCUME%7E1/E5900538/LOCALS%7E1/Temp/moz-screenshot.png