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Altera_Forum
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18 years ago

Warning: Converting TRI node that feeds logic to an OR gate

I am in the process of upgrading from QII 5.0 to QII 7.1 and I am facing some problems. My design is fairly large. One of the modules that I know is not working properly is a module that interfaces...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Yes, that looks correct(although I don't have the full picture). Are the pins declared as being type bidir? I've seen that be an issue before.

Can you look in the Technology Map Viewer or the Chip Editor and see if the tri-state is being used for those pins?