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Altera_Forum's avatar
Altera_Forum
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14 years ago

Warning (18029): Output pin [...] cannot be tri-stated

Hi,

I get the following warning (for each line of "Data") in my design:

"Warning (18029): Output pin "_subnet_pin_406" driven by bidirectional pin "Data(0)" cannot be tri-stated"

"Data" is a bidirectional bus, the Pins should be tristated, when the FPGA makes a read access. I'm working with a Cyclone III and Quartus 12.0SP2. The Design seems to work on my board, and the RLT schematic shows tristate buffers at the outputs.

The Quartus help says:

CAUSE:

The specified output pin is driven by both the specified bidirectional pin and tri-stated logic. However, the current device does not support a tri-stated output pin. When the output pin is not driven by either the logic or the bidirectional pin, its output value is undefined.

ACTION:

If the output pin is always driven by either the logic or the bidirectional pin, no action is required. Otherwise, insert an extra tri-state buffer before the output pin.

I don't understand, what the quartus help wants to say. The sentence doesn't make much sense to me... ;-)

can anyone help me to understand the warning?

Regards,

Ego

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi, please post code or schema to help you more.

    (How do you declare those pins ?)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Hi, please post code or schema to help you more.

    (How do you declare those pins ?)

    --- Quote End ---

    I also have this problem.I doubt that what Output pin "_subnet_pin_406" means. Where is _subnet_pin_406 ?I can't find it in the design.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    I also have this problem. I'm using Quartus 13.0 and I'm targetting a Cyclone IV GX.

    I simplified my design to this: 

    
escc_data_out		<= "00010100";
ESCC_DATA	<= escc_data_out   when blink   = '0' else "ZZZZZZZZ";

    ESCC_DATA is also used as an input somewhere in the design.

    I get some warning for the whole bus: 

    Warning (18029): Output pin "pre_syn.bp.ESCC_CTRL_ESCC_DATA_IN_0_" driven by bidirectional pin "ESCC_DATA" cannot be tri-stated

    The RTL view seems correct:

    https://www.alteraforum.com/forum/attachment.php?attachmentid=8278

    However, the post mapping view shows some strange things. Sometimes the blink signal is connected to the tri-state buffer enable pin, sometimes it is connected to the tri-state buffer input.

    If I don't use ESCC_DATA as an input, I don't have warnings anymore.

    Any idea ?

    Franck.