Warning (14320): Synthesized away node -> what does it mean?

I have been receiving the following warnings when I generate an Altera PLL:

Warning (14284): Synthesized away the following node(s):

Warning (14285): Synthesized away the following PLL node(s):

Warning (14320): Synthesized away node "PLL_Main:PLL_inst|PLL_Main_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[2]"

Warning (14284): Synthesized away the following node(s):

Warning (14285): Synthesized away the following PLL node(s):

Warning (14320): Synthesized away node "PLL_Main:PLL_inst|PLL_Main_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[1]"

All the output clocks get synthesized away, except for one. I have triple checked that all the output clocks (I tried with 2, 3, 4 clocks at different times) ARE connected to modules which do get synthesized. Further, I get the following clock created, no idea from where:

PLL_Main:PLL_inst|PLL_Main_0002:pll_main_inst|altera_pll:altera_pll_i|fboutclk_wire[0]

I have not had this problem in the past, where I used the PLL Megafunction to generate clocks. I am currently using Quartus 17.1 . Do any specific constraints need to be added in the SDC file to circumvent this?

Thanks