Forum Discussion
Altera_Forum
Honored Contributor
8 years agoIf it got synthesised away, it means the synthesis tool determined that the node has no effect on any outputs, so has removed it from the design. This often occurs to unconnected nets, nets that are stuck low or high, registers not connected to a clock (or the clock is stuck at 1/0), registers with enable always low or registers with reset always asserted. If you were not expecting this, you will need to review the warnings and code to determine why the node was removed.
Receiving the warning is ok, if you are expecting it. Many designers use the fact above to have parts of the design deliberately removed by leaving ports disconected, or generics set in such a way that only uses part of a design. The nets will no longer exist if they have been removed. They may exist on the RTL viewer, but wont exists on the mapped view and wont exist in the final design.