Warning (13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
There are a few components impacted by this warning. Doing a search on the Altera Site, this is what it has to say:
CAUSE:
One or more registers in the design have one of the following conditions:
The current device family does not support any of these conditions. As a result, Analysis & Synthesis converts the register to equivalent circuits with a latch, a register and logic, and the resulting register powers-up to an undefined state (X). In addition to that, dev_clrn (
http://quartushelp.altera.com/13.1/mergedprojects/comp/comp/comp_db_device_pin_options.htm) places the register in an undefined state, and the resulting circuit is prone to glitches because the there are different paths from the asynchronous signals to the output of the logic representing the register. Since these paths have different delays, glitches can occur, especially if the asynchronous signals are coming from combinational logic, or if the register is feeding combinational logic. See submessages for details.
ACTION:
No action is required. If you want to prevent glitches, put KEEP attributes on the asynchronous signals that feeds the register, and on the register itself. This action is necessary only if the asynchronous signals come from combinational logic or if the register feeds combinational logic. Make sure that you perform timing simulation to verify that no unexpected glitches occur.
The main component impacted (largest number of originating warnings) is a 16-bit shift register with asynchronous load. An AND gate feeds the Load Signal. I put a /* synthesis keep */ on the load line but this did not resolve the issue. Any suggestions on this?
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