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Altera_Forum
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10 years ago

Wand problem

I am new to Quartus II trying to use "wand" in Verilog as I have been always using on other FPGA development tools...

I get "signal has multiple drivers"....

This for MAX10 is there limitations or options?? Neither run into this problem in 20 years.

Thanks Guy

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    What devices have you been using? Wired and is not possible inside an FPGA, and hasnt been for a very long time (if ever).

    If it worked in other tools, it would have been creating logic to emulate wired and.

    Basically - dont use it.
  • Altera_Forum's avatar
    Altera_Forum
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    hi Tricky, i read some doc the wind structural data type is seems belongs to product X..... hehe

  • Altera_Forum's avatar
    Altera_Forum
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    You can say Xilinx here.

    There are differences between the two tools, but the technology is roughly the same. So Xilinx decides to support wand and Quartus doesnt. Either way, it doesnt synthesis to wired and.

    So if you want to make it work in Altera, you cannot use wand.
  • Altera_Forum's avatar
    Altera_Forum
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    hi guyp87, as the our forum master mentioned, there is a give and take occasion when we here to choose either Xilink or Altera.

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    Altera_Forum
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    --- Quote Start ---

    okay... looks like you are another expert user from X background....that structural data type seems only for X only...

    Maybe you can try to migrate most of the design from the below guide.

    http://www.pldworld.com/_altera/html/_sw/qts-x2a_migration.html

    https://www.altera.com/en_us/pdfs/literature/an/an307.pdf

    --- Quote End ---

    Thanks a lot tony_stark and Tricky!!

    I cannot see reference to wand or wor construct in the documents you point me into:)

    I have used them on all FPGA (including Lattice, Actel and Xilinx) it makes the coding more readable when lot of parallel elements...I used Altera also in the past and wand was okay in 2009 !

    Surprising...it should be an option for the Quartus 2 on the link below Verilog HDL reference from Altera it mentions in section 3.7.2 that it is indeed a supported construct....

    http://quartushelp.altera.com/14.0/mergedprojects/hdl/vlog/vlog_list_support.htm

    That said I know how to go around just lot of typing when putting 100 neurons on a FPGA ;)

    Thanks again

    Guy